1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device.
2. Related Art
Semiconductor devices have been proposed in which a test pad and a bump electrode pad having a bump electrode formed thereon are formed on a substrate (Japanese Patent Application Laid-Open (JP-A) Nos. 2001-127256, 2002-90422, 2006-210438, and 7-201886).
In the semiconductor devices, it is possible to contact a probe of a test device with the test pad to measure the characteristics of the semiconductor device. When the probe comes into direct contact with the bump electrode, the bump electrode is deformed, which causes a connection error to other electronic apparatuses. When the test pad is formed, it is possible to solve the above issue.
As shown in FIGS. 8 to 10, the semiconductor device is manufactured by, for example, the following method.
As shown in FIG. 8, an uppermost interconnect layer 103 is formed on a substrate 100, and a first passivation film 101 is formed on the uppermost interconnect layer 103. Then, openings are formed in the first passivation film 101. A portion (a probe contact region and a bonding region) of the uppermost interconnect layer 103 is exposed through the openings.
Then, a barrier metal film 102 is formed, and a resist 104 is provided to form a bump 105 on the bonding region, as shown in FIG. 9.
Then, as shown in FIG. 10, the barrier metal film 102 on the probe contact region is removed (see JP-A No. 2006-210438).
In addition, the following manufacturing method has been proposed. The manufacturing method will be described with reference to FIGS. 11 to 14.
An uppermost interconnect layer 103 is formed on a substrate 100, and a first passivation film 101 is formed on the uppermost interconnect layer 103. Then, openings are formed in the first passivation film 101 (see FIG. 11). Then, a probe comes into contact with a probe contact region 103A of the uppermost interconnect layer 103 exposed through the opening of the first passivation film 101 to perform a test (see FIG. 12). In this case, a probe contact mark H is formed in the probe contact region 103A.
Then, as shown in FIG. 13, a second passivation film 106 is formed and the second passivation film 106 on a bonding region 103B is removed. Then, as shown in FIG. 14, a barrier metal 107 is formed and the barrier metal 107 in regions other than the bonding region 103B is removed. Then, a bump 108 is formed on the bonding region 103B (see JP-A No. 2006-210438).
The present inventor has recognized as follows. In the method disclosed in JP-A No. 2006-210438, when the barrier metal film 102 on the probe contact region 103A of the uppermost interconnect layer 103 is completely removed, the uppermost interconnect layer 103 is also etched, which makes it difficult to normally perform a test.
In the method disclosed in JP-A No. 2006-210438, finally, the probe contact region 103A is covered with the second passivation film 106. Therefore, only before the second passivation film 106 is formed, a test can be performed. However, it is difficult to perform the test after the semiconductor device is manufactured. In the semiconductor device disclosed in JP-A No. 2006-210438, an essential structure is to cover the probe contact region 103A with the second passivation film 106.